Innovations in 3D integration
21st century applications, such as large-language models (LLMs) or immersive computer vision with edge AI, have exploded in size and ambition, demanding large gains in computing performance that traditional transistor miniaturization can no longer deliver. To exacerbate this challenge, modern systems spend vast amounts of time and energy moving data between computing logic and memory without performing useful computation (memory wall).
Three-dimensional (3D) integration offers an escape route by (a) massively increasing the logic and memory capacity within the same chip footprint through stacking multiple vertical tiers, and (b) leveraging fine-grained, dense vertical connections—such as monolithic 3D (M3D) integration or hybrid bonding (HB)—to dramatically improve bandwidth and lower latency between compute and memory.
Our research focuses on enabling the technology, circuit, and architectural foundations for future 3D-integrated computing systems.
Ultra-Dense 3D Logic+Memory Integration
Our research develops monolithic 3D (M3D) systems that combine high-performance logic with dense, low-energy memory in vertically stacked tiers. On the logic side, we focus on beyond-silicon device technologies such as carbon nanotube FETs (CNFETs) that deliver high performance at low supply voltages while being fully compatible with back-end-of-line (BEOL) 3D integration alongside today’s silicon CMOS logic. On the memory side, we explore dense, energy-efficient 3D memories such as RRAM that can be co-integrated at fine pitches directly above silicon and paired with BEOL 3D logic. Our prior work demonstrated the first silicon-compatible BEOL 3D CNFET process and used it to build some of the most advanced digital electronics with CNFETs — including the first CNFET-based RISC-V microprocessor and the first CNFET + CMOS M3D system. These advances transitioned from the lab to industrial fabs and foundries, where we co-integrated CNFET logic with RRAM and silicon CMOS in a monolithic 3D stack.
By stacking high-performance logic with efficient, ultra-dense memory, these M3D architectures can drastically reduce data movement overheads and achieve large improvements in energy–delay product (EDP) for data-intensive applications such as AI accelerators compared to iso-footprint 2D systems.
3D Power Delivery and Thermal Management
As 3D tiers of compute and memory scale, thermal management and power delivery become critical bottlenecks. Conventional ultra-low-κ dielectrics trap heat and exacerbate IR drop, limiting the number of reliable 3D tiers. To address this, our research develops co-designed solutions that simultaneously improve heat extraction and power integrity. Our approaches focus on identifying new high-thermal conductivity back-end-of-line (BEOL) dielectrics combined with optimized 3D IC power delivery networks to enable multiple high-power 3D compute tiers—critical for next-generation compute-bound workloads.
These efforts provide the technology and circuit foundations for scaling ultra-dense 3D systems with reliable thermal and power delivery.