CMP-aware CAD of integrated circuits (ICs)

In electrical & computer engineering, computer-aided design (CAD) engineers build integrated circuit (IC) designs without knowledge of the semiconductor manufacturing processes (designed by mechanical engineers) that cause variations. In collaboration with the Carnegie Mellon Center for Silicon Systems Implementation (CSSI), this work aims to make them “aware”.

PFTL Researcher(s): TBA, Ryan Comes, Jeremiah Mpagazehe, and Travis Iwanaga

Method(s) employed: Layout design, Physics-based modeling of CMP, CMOS processing and nanofabrication

Sponsor(s): NSF CISE (CPA)

Reference(s): N/A